A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge in a specified portion of a substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing the charge at the storage region. Photo-charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524 and 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
FIG. 1 is an illustration of a conventional four transistor (4T) pixel 100 and an associated load circuit 120 (shown as a current source). The pixel 100 includes a light sensitive element 101, shown as a photodiode, a floating diffusion region C, and four transistors: a transfer transistor 111, a reset transistor 112, a first source follower transistor 113, and a row select transistor 114. The pixel 100 accepts a TX control signal for controlling the conductivity of the transfer transistor 111, a RS control signal for controlling the conductivity of the reset transistor 112, and a SEL control signal for controlling the conductivity of the row select transistor 114. The charge at the floating diffusion region C controls the conductivity of the first source follower transistor 113. The output of the source follow transistor 113 is presented to the load circuit 120 through the row select transistor 114, which outputs a pixel signal at node B, when the row select transistor 114 is conducting (i.e., when SEL is asserted).
The states of the transfer and reset transistors 111, 112 determine whether the floating diffusion region C is coupled to the light sensitive element 101 for receiving photo generated charge generated by the light sensitive element 101 during a charge integration period, or a source of pixel power Vaapix from node A during a reset period.
The pixel 100 is operated as follows. The SEL control signal is asserted to cause the row select transistor 114 to conduct. At the same time, the RS control signal is asserted while the TX control signal is not asserted. This couples the floating diffusion region C to the pixel power Vaapix at node A, and resets the voltage at node C to the an initial voltage. The pixel 100 outputs a reset signal VRST to the load circuit 120. Node B is coupled between the row select transistor 114 and the load circuit 120 and serves as an input to a sample and hold circuit (not shown ) that samples and holds the pixel reset voltage VRST.
After the reset signal VRST has been output, the RS control signal is deasserted. The light sensitive element 101 has been exposed to incident light and accumulates charge on the level of the incident light during a charge integration period. After the charge integration period and the output of the signal VRST, the TX control signal is asserted. This couples the floating diffusion region C to the light sensitive element 101. Charge flows through the transfer transistor 111 and diminishes the voltage at the floating diffusion region C. The pixel 100 outputs a photo signal VSIG to the load circuit 120 which appears at node B and is sampled by the sample and hold circuit (not shown). The reset and photo signals VRST, VSIG are different components of the overall pixel output (i.e., Voutput=VRST−VSIG).
A pixel 100 is susceptible to a type of distortion known as eclipsing. Eclipsing refers to the distortion arising when a pixel outputs a pixel signal corresponding to a dark pixel even though bright light is incident upon the pixel. Eclipsing can occur when a pixel is exposed to bright light, as the light sensitive element 101 can produce a large quantity of photogenerated charge. While the pixel 100 is outputting the reset signal VRST, a portion of the photogenerated charge produced by the light sensitive element 101 during an ongoing integration period may spill over the transfer transistor 111 into the floating diffusion node C. This diminishes the reset voltage at the floating diffusion node and can causes the pixel 100 to output an incorrect (i.e., diminished voltage) reset signal VRST. This, in turn, can cause the reset and photo signals VRST, VSIG to be nearly the same voltage. For example, the photo and reset signals VRST, VSIG may each be approximately 0 volts. The pixel output (VRST−VSIG) can therefore become approximately 0 volts, which corresponds to an output voltage normally associated with a dark pixel.
An anti-eclipse circuit can be used to minimize the effect of eclipsing. For example, since during an eclipse a pixel's reset voltage tends to drop towards zero volts, an anti-eclipse circuit can monitor the voltage level of the reset signal. If the voltage level drops below a threshold voltage, the anti-eclipse circuit can assume that the eclipsing may occur (or is occurring) and then correct the voltage level of the reset signal by pulling the reset level up to a correction voltage, thereby minimizing the eclipse effect.
FIG. 2 is an illustration of the pixel 100, its load circuit 120, and a conventional anti-eclipse circuit 230 for overcoming the above-described eclipse problem. The anti-eclipse circuit 230 comprises a second source follower transistor 231 coupled in series with a switching transistor 232. The output of the switching transistor 232 is coupled in parallel with the output of the pixel 100 to the input of the load circuit 120 (i.e., to node B). The second source follower transistor 231 has one source/drain coupled to the pixel power Vaapix and another source/drain terminal coupled to the switching transistor 232. The second source follower transistor 231 is biased with a VREF control signal. The conductivity of the switching transistor 232 is controlled by a SHR (sample and hold reset) control signal which is used to sample and hold the VRST signal. The VREF voltage level is set so that if the voltage on the floating diffusion region C degrades while the reset signal VRST is being output, the second source follower transistor 231 conducts and pulls the voltage at node B up to VREF minus the threshold voltage of the second source follower transistor 231. One limitation of the anti-eclipse circuit 230 is to have a sufficient margin against possible variations of VRST. VRST is affected by threshold voltage variations of both reset transistor 112 and source follower transistor 113. In addition, temperature change, voltage change of VAA and a high level of the RS control pulse affect VRST. When anti-eclipsing is not needed, as in normal exposure conditions, current that flows through the second source follower transistor 231 should be zero in order to avoid any contribution from the anti-eclipse circuit 230. Therefore, VREF should be chosen as a sufficiently low voltage supposing a minimum value VRST variation, which results in reduced VREF voltage and causes difficulty in obtaining a sufficient output level for anti-eclipsing.
Accordingly, there is a need and desire for an improved anti-eclipse circuit for imagers.